This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In modern circuit design, tracking wordline behavior is important for a memory complier controlled by a self-timed internal clock. Some circuit designers have attempted to track the behaviour of a real wordline array by using a dummy array. The dummy array can be a part of a memory cell array, and the dummy array can be driven by a replica of a real wordline driver. However, using a dummy array can use additional area on chip for the dummy array. Thus, area overhead is increased with this approach, which reduces chip layout efficiency. In other cases, some circuit designers have attempted to track the behaviour of a real wordline array by using a metal wire and gate load with periphery logic devices. Unfortunately, area overhead is also increased, and the dummy array along with the metal wire and the gate loads of periphery logic devices may not accurately track the behaviour of the real wordline array. Thus, the resultant inaccurate tracking can cause functional problems during read and/or write operations.